Consider our simple 1 cycle-per-instruction ARM architecture

Consider our simple 1 cycle-per-instruction ARM architecture. Is x6 the register file’s “Source 1,” “Source 2,” or “Destination”? Transcribed Image Text: 64-bit adder>
inst[23.4]
sign
extend
left shift 2
Branch
DECODER
inst[31.21]
inst[15.10]
delay 1
clock cycle
WriteReg
Reg2Sel
REGISTER FILE
Src1
inst[9..5]
Şource 1
>Zero
WriteMem
ReadMem
Read Data 1
INSTRUCTION
inst[20.16]
Src2Sel
ALU
DATA MEMORY
MEMORY
Şource 2
Result
>Address
PC
Read Data 2
Read
Address
Src2
inst[4.0]
Destination
Read Data
Instruction
Write Data
Write Data
WriteSel
inst[21..10]
zero/sign
extend
inst[20..12]
sign
extend
Consider our simple 1 cycle-per-instruction ARM architecture. Suppose that PC=0x12343210, where the encoding for the
ARM instruction str x7, [x6, 20] is stored. As a reminder, the str R, [R„D] instruction stores the contents of R_ to memory
location [R„D], and the address of [R„D] is determined by adding the displacement value D to the contents of register R,.
Is x6 the register file’s “Source 1,” “Source 2,” or “Destination”?
O Source 2
O Source 1
O Destination

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